The present invention relates generally to the realization of RF passive elements and interconnect metallization with very low parasitic capacitance to an underlying conductive substrate and adjacent metallization through the use of conductive, three dimensional, dynamic shielding. More particularly, the subject invention pertains to three dimensional, dynamically shielded metal elements such as inductors, MIM (metal-insulator-metal) capacitors, resistors, wirebond pads, and stable bias lines constructed in the interconnect metallization layers (Back End Of Line, BEOL) of a monolithic, integrated circuit. This three dimensional shielding of the BEOL elements (inductors, capacitors, resistors, etc.) reduces or eliminates the parasitic capacitive coupling between the element and the conductive substrate. Additionally, parasitic fringe capacitance coupling between the specific BEOL element and adjacent areas of metallization is reduced or eliminated, generally increasing the elements self-resonance frequency and reducing crosstalk between BEOL elements.
One area of particular interest for BEOL passive elements centers on the improvement of inductor elements. Prior art implementations for BEOL inductor elements have utilized a buffered drive of adjacent spiral inductive elements to achieve a higher quality factor (Q), and have required complicated processing or many additional accessory functional elements, such as a variable attenuator and a variable phase shifter. These prior art implementations of shielded inductors have attempted to achieve a higher Q by increasing the magnetic flux coupling of the inductor (Yeung, et. al., “Design Considerations for extremely High Q Integrated Inductors and Their Application in CMOS RF Power Amplifier”, IEEE Proceedings, RAWCON, 1998).
Another area of particular interest pertaining to BEOL elements concentrates on the reduction of parasitic capacitance between interconnect elements and an underlying conductive substrate or adjacent metallization. Prior art implementations have utilized a planar shield, underneath the interconnect, driven by a buffer to minimize capacitive coupling to a conductive substrate (U.S. Pat. No. 5,151,775, Hadwin).